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NT7703
160 Output LCD Segment/Common Driver
Features
(Segment mode) ! Shift Clock frequency: 14 MHz (Max.) (VDD = 5V 10%) 8 MHz (Max.) (VDD = 2.5V - 4.5V) ! Adopts a data bus system ! 4-bit / 8-bit parallel input modes are selectable with a mode (MD) pin ! Automatic transfer function with an enable signal ! Automatic counting function when in "chip select" mode, which causes the internal clock to be stopped by automatically counting 160 bits of input data (Common mode) ! Shift clock frequency: 4.0MHz (Max.) ! Built-in 160-bits bidirectional shift register (divisible into 80-bits x 2) ! Available in a single mode (160-bits shift register) or in a dual mode (80-bits shift register x 2) 1. Y1 Y160 Single mode 2. Y160 Y1 Single mode 3. Y1 Y80, Y81 Y160 Dual mode 4. Y160 Y81, Y80 Y1 Dual mode The above 4 shift directions are pin-selectable (Both segment mode and common mode) ! Supply voltage for LCD drive: 15.0 to 30.0V ! Number of LCD driver outputs: 160 ! Low output impedance ! Low power consumption ! Supply voltage for the logic system: +2.5 to +5.5V ! COMS process ! Package: Gold bump die / 186 Pin TCP (Tape Carrier Package) ! Not designed or rated as radiation hardened
General Description
The NT7703 is a 160-bit output segment/common driver LSI suitable for driving the large scale dot matrix LCD panels used by PDA's, personal computers and work stations for example. Through the use of COG technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The NT7703 is good as both a segment driver and a common driver, and a low power consuming, highprecision LCD panel display can be assembled using the NT7703. In the segment mode, the data input is selected as 4bit parallel input mode or as 8bit parallel input mode by a mode (MD) pin. In common mode, the data input/output pins are bi-directional and the four data shift directions are pinselectable.
Pin Configuration
D U M M Y D U M M Y D U M M Y D U M M Y Y 1 6 0 Y 1 5 9 Y 1 5 8 Y 1 5 7 Y 1 5 6 Y 1 5 5 Y 8 3 Y 8 2 Y 8 1 Y 8 0 Y 7 9 Y 7 8 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 D U M M Y D U M M Y D U M M Y D U M M Y
186 185 184 183 182 181
109 108 107 106 105 104
32 31 30 29 28 27
NT7703
1 V 0 L
2 V 1 2 L
3 V 4 3 L
4 V S S / V 5 L
5 L / R
6 V D D
7 S / C
8 E I O 2
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 X C K D I S P O F F L P E I O 1 F R M D V S S / V 5 R V 4 3 R V 1 2 R V 0 R
1
V1.0
NT7703
Pad Configuration
272 x x 145 x x
273
144
NT7703
288 x 1
ALK_L
Dummy Pad
x
ALK_R
129 x
128
Block Diagram
V0R V12R V43R V5R
Y1 Y2 Y159 Y160
FR Level Shifter
DISPOFF
V5L
160 Bits 4 Level Driver
/160
V43L V12L
160 Bits Level Shifter
EIO1 V5R Active Control EIO2
/16 /16 /16 /16 /16 /16 /16 /16 /16 /16 /160
V0L
160 Bits Line Latch/Shift Register
LP XCK
8Bits x 2 Data Latch Control Logic
Data Latch Control
L/R MD S/C
/8
SP Conversion & Data Control (4 to 8 or 8 to 8)
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
VDD
VSS VSS
2
NT7703
Pad Description
Pad No. 1-7 8 - 12 13 - 17 18 - 22 23 - 39 40 - 41 42 - 57 58 - 59 60 - 61 62, 63 - 74, 75 76 - 77 78 - 79 80 - 81 82 - 83 84 - 85 86 - 87 88 - 89 90 - 106 107 - 111 112 - 116 117 - 121 122 - 128 129 - 288 Designation V0L V12L V43L V5L VSS L/R VDD S/C EIO2 D0 - D6 D7 XCK DISPOFF LP EIO1 FR MD VSS V5R V43R V12R V0R Y1 - Y160 I/O P P P P P I P I I/O I I I I I I/O I I P P P P P O Description Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Ground (0V), these two pads must be connected to each other Display data shift direction selection Power supply for the logic system (+2.5 to + 5.5V) Segment mode / common mode selection Input / output for chip select or data of shift register Display data input for segment mode Display data input for Segment mode / Dual mode data input Display data shift clock input for segment mode Control input for deselect output level Latch pulse input / shift clock input for the shift register Input / output for chip select or data of the shift register AC-converting signal input for LCD driver waveform Mode selection input Ground (0V), these two pads must be connected to each other Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver LCD driver output
3
NT7703
Input / Output Circuits
VDD
I
Input Signal
Applicable Pins L/R, S/C, D0 - D6, DISPOFF , LP, FR, MD
VSS Input Circuit (1)
VDD
I Control Signal
Input Signal
Applicable Pins D7, XCK
VSS
VSS Input Circuit (2)
4
NT7703
VDD
Input Signal Control Signal
VSS VDD
VSS Output Signal
I/O
Control Signal
VSS
Applicable Pins EIO1, EIO2
Input / Output Circuit
V0
V12
Control Signal 1 O Control Signal 3
Control Signal 2
Control Signal 4
Applicable Pins Y1 to Y160
V43 VSS V5
LCD Driver Output circuit
5
NT7703
Pad Description
Segment mode Symbol VDD VSS VOR, VOL V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects from +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias " Normally, the bias voltage used is set by a resistor divider " Ensure that the voltages are set such that VSS V5 < V43 < V12 < V0 " To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y160, externally connect ViR and ViL (I = 0, 12, 43) Input pin for display data " In 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to VSS or VDD " In 8-bit parallel input mode, input data into the 8 pins D0 - D7 Clock input pin for taking display data " Data is read on the falling edge of the clock pulse Latch pulse input pin for display data " Data is latched on the falling edge of the clock pulse Direction selection pin for reading display data " When set to VSS level "L", data is read sequentially from Y160 to Y1 " When set to VDD level "H", data is read sequentially from Y1 to Y160 Control input pin for output deselect level " The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the LCD driver circuit " When set to VSS level "L", the LCD driver output pins (Y1 - Yl60) are set to level V5 " When DISPOFF is set to "L", the contents of the line latch are reset, but the display data in the data latch DISPOFF are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver outputs the deselect level (V12 or V43), then outputs the contents of the date latch onto the next falling edge of the LP At that time, if the DISPOFF removal time can not keep in regulation with what is shown on the AC characteristics, then it can not output the reading data correctly AC signal input for LCD driving waveform " The input signal is level-shifted from the logic voltage level to the driver voltage level, and controls LCD driver circuit " It normally inputs a frame inversion signal The LCD driver output pin's output voltage level can be set to the line latch output signal and the FR signal Mode selection pin " When set to VSS level "L", 4-bit parallel input mode is set " When set to VDD level "H", 8-bit parallel input mode is set
D0 - D7
XCK LP
L/R
FR
MD
6
NT7703
Segment mode continued Symbol S/C Function Segment mode/common mode selection pin " When set to VDD level "H", segment mode is set " When set to VSS level "L", common mode is set Input/output pin for chip selection " When L/R input is at VSS level "L", EIO1 is set for output, and EIO2 is set for input " When L/R input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output " During output, it is set to "H" when LP* XCK is "H" and then after 160-bits of data have been read, it is set to "L" for one cycle (from falling edge to falling edge of XCK), after which it returns to "H" " During input, after the LP signal is input, the chip is selected while EI is set to "L". After 160-bits of data have been read, the chip is deselected LCD driver output pins These correspond directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output
EIO1, EIO2
Y1 - Y160
Common mode Symbol VDD VSS V0R, V0L V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects from +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias. " Normally, the bias voltage used is set by a resistor divider " Ensure that the voltages are set such that VSS V5 EIO1
EIO2
LP
L/R
7
NT7703
Common mode continued Symbol Function Control input pin for output deselect level " The input signal is level-shifted from the logic voltage level to the LCD driver voltage level and it controls the LCD driver circuit " When set to VSS level "L", the LCD driver output pins (Y1 - Y160) are set to level V5 DISPOFF " While set to "L", the contents of the shift resister are reset and are not reading data. When the DISPOFF function is canceled, the driver outputs deselect level (V12 or V34), and the shift data is read on the falling edge of the LP. At that time, if the DISPOFF removal time can not keep regulation with what is shown on the AC characteristics, then the shift data is not read correctly AC signal input for LCD driving waveform " The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the LCD driver circuit " Normally, it inputs a frame inversion signal The LCD driver output pin's output voltage level can be set using the shift register output signal and the FR signal Mode selection pin " When set to VSS level "L", Single Mode operation is selected. When set to VDD level "H", Dual Mode operation is selected Dual Mode data input pin " According to the data shift direction of the data shift register, data can be input starting from the 81st bit When the chip is used in Dual Mode, D7 will be pulled-down When the chip is used in Single Mode, D7 won't be pulled-down Segment mode/common mode selection pin " When set to VSS level "L", common mode is set Not used " Connect D0-D6 to VSS or VDD. Avoid floating Not used " XCK is pulled-down in common mode, so connect to VSS or leave open LCD driver output pins " These correspond directly to each bit of the shift register, one level (V0, V12, V43, or V5) is selected and output
FR
MD
D7
S/C D0 - D6 XCK
Y1 - Y160
8
NT7703
Functional Description
1. Block description 1.1. Active Control In segment mode, it controls the selection or deselection of the chip. Following a LP signal input and after the select signal is input, a select signal is generated internally until 160 bits of data have been read in. Once data input has been completed, a select signal for the cascade connection is output, and the ship is deselected. In common mode, it controls the input/output data of the bidirectional pins. 1.2. SP Conversion & Data Control In segment mode, it keeps input data, which are 2 clocks of XCK at 4-bit parallel mode in the latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel mode in the latch circuit, after which they are put on the internal data bus 8 bits at a time. 1.3. Data Latch Control In segment mode, it selects the state of the data latch, which reads in the data bus signals. The shift direction is controlled by the control logic and for every 16 bits of data read in, the selection signal shifts one bit, based on the state of the control circuit. 1.4. Data Latch In segment mode, it latches the data onto the data bus. The latched state of each LCD driver output pin is controlled by the control logic and the data latch control. 160 bits of data are read in 20 sets of 8 bits. 1.5. Line Latch / Shift Register In segment mode, it ensures that all 160 bits which have been read into the data latch are simultaneously latched on to the falling edge of the LP signal, and output to the level shift block. In common mode, shifts data from the data input pin on to the falling edge of the LP signal. 1.6. Level Shifter It ensures the logic voltage signal is level-shifted to the LCD driver voltage level, and output to the driver block. 1.7. 4-Level Driver It drives the LCD driver output pins from the line latch/shift register data, selecting one of 4 levels (V0, V12, V43, V5) based on the S/C, FR and DISPOFF signals. 1.8. Control Logic It controls the operation of each block. In segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission are controlled, 160 bits of data are read in, and the chip is deselected. In common mode, it controls the direction of the data shift.
9
NT7703
2. LCD Driver Output Voltage Level The relationship between the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table below: 2.1. Segment Mode FR L L H H X Latch Data L H L H X DISPOFF H H H H L Driver Output Voltage Level (Y1 - Y160) V43 V5 V12 V0 V5
Here, VSS V5 < V43 < V12 Here, VSS V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular voltage, which is assigned by specification for each power pin. That time "Don't care" should be fixed to "H" or "L", avoiding floating.
10
NT7703
3. Relationship between the Display Data and Driver Output Pins 3.1. Segment Mode: (a) 4-bit Parallel Mode MD L/R EIO1 EIO2 Data Input D0 D1 D2 D3 D0 D1 D2 D3 40clock Y1 Y2 Y3 Y4 Y160 Y159 Y158 Y157 39clock Y5 Y6 Y7 Y8 Y156 Y155 Y154 Y153 Number of Clock 38clcok ~ 3clock ~ Y9 Y149 ~ Y10 Y150 ~ Y11 Y151 ~ Y12 Y152 ~ Y152 Y12 ~ Y151 Y11 ~ Y150 Y10 ~ Y149 Y9 2clock Y153 Y154 Y155 Y156 Y8 Y7 Y6 Y5 1clock Y157 Y158 Y159 Y160 Y4 Y3 Y2 Y1
L
L
Output
Input
L
H
Input
Output
(b) 8-bit Parallel Mode MD L/R EIO1 EIO2 Data Input D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 20clock Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 19clock Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y152 Y151 Y150 Y149 Y148 Y147 Y146 Y145 Number of Clock 18clcok ~ 3clock Y17 ~ Y137 Y18 ~ Y138 Y19 ~ Y139 Y20 ~ Y140 Y21 ~ Y141 Y22 ~ Y142 Y23 ~ Y143 Y24 ~ Y144 Y144 ~ Y24 Y143 ~ Y23 Y142 ~ Y22 Y141 ~ Y21 Y140 ~ Y20 Y139 ~ Y19 Y138 ~ Y18 Y137 ~ Y17 2clock Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 1clock Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1
H
L
Output
Input
H
H
Input
Output
11
NT7703
3.2. Common Mode MD L (Single) L/R L (shift to left) H (shift to right) L (shift to left) H (Dual) H (shift to right) Data Transfer Direction Y160 to Y1 Y1 to Y160 Y160 to Y81 Y80 to Y1 Y1 to Y80 Y81 to Y160 EIO1 Output Input Output EIO2 Input Output Input D7 X X Input
Input
Output
Input
Here, L: VSS (0V), H: VDD (+2.5V to +5.5V), X: Don't care Note: "Don't care" should be fixed to "H" or "L", avoiding floating.
12
NT7703
4. Connection Examples of Segment Drivers 4.1. Case of L/R = "L"
first data (data taking flow) Y160 ---------------------->Y1 Y160 ---------------------->Y1 Y160 ---------------------->Y1 last data
EIO2
EIO1 L/R DI0 - DI7
EIO2
EIO1 L/R DI0 - DI7
EIO2
EIO1 L/R DI0 - DI7
XCK
XCK
XCK
MD
MD
MD
FR
FR
XCK LP MD FR D0 - D7 VSS /8
4.2 Case of L/R = "H"
VDD D0 - D7 FR MD LP XCK /8
XCK
XCK
FR
LP
LP
LP
DI0 - DI7
DI0 - DI7
L/R VSS EIO1 EIO2
L/R EIO1 EIO2
L/R EIO1 EIO2
Y1 ---------------------->Y160 (data taking flow) first data
Y1 ---------------------->Y160
Y1 ---------------------->Y160
DI0 - DI7
last data
13
XCK
MD
MD
MD
FR
FR
FR
LP
LP
LP
NT7703
5. Timing Waveform of 4-Device Cascade Connection of Segment Drivers.
FR
LP
XCK
First data D0 - D7 n12 device A EI (device A) n12 device B n12 device C n12 device D
Last data n12
H L
EO (device A)
EO (device B)
EO (device C) n: 4-bit parallel mode 40 8-bit parallel mode 20
14
NT7703
6. Connection Examples for Common Drivers
First Last
Y160
Y1
Y160
Y1
Y160
Y1
D
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
MD
EIO1
L/R
L/R
L/R
MD
MD
MD
FR
D7
D7
FR
LP VSS(VDD) VSS VSS DISPOFF FR
Single Mode (Shifting towards the left)
FR CS DISPOFF VDD VSS VSS(VDD) LP
FR
D7
LP
LP
LP
FR
DI7 EIO2 LP
DISPOFF
DISPOFF
DI
EIO1
EIO2
EIO1
EIO2
EIO1
Y1
Y160
Y1
Y160
Y1
DISPOFF
MD
MD
FR
FR
DI7
DI7
L/R
L/R
CS
CS
L/R
LP
LP
CS
Y160
First
Last
Single Mode (Sifting towards the right)
15
NT7703
First1 Last1 First2 Last2
Y160
Y1
Y160
Y81
Y80
Y1
Y160
Y1
D1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
D7
EIO1
L/R
L/R
L/R
MD
MD
MD
FR
FR
D7
D7
LP D2 VSS (VDD) VDD VSS DISPOFF FR
Dual mode (Shifting towards the left)
FR DISPOFF VDD VDD VSS (VDD) D2 LP
MD
MD
D7
LP
LP
LP
MD
LP
LP
L/R
L/R
DISPOFF
DISPOFF
D1
EIO1
EIO2
EIO1
EIO2
EIO1
DISPOFF
L/R
D7
FR
FR
D7
FR
EIO2
Y1
Y160
Y1
Y80
Y81
Y160
Y1
Y160
First1
Last1 First2
Last2
Dual mode (Shifting towards the right)
16
LP
FR
NT7703
7. Precaution Be careful when connecting or disconnecting the power This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occur if voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The details are as follows: ! When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power. ! We recommend that you connect a serial resistor (50-100) or fuse to the LCD driver power V0 of the system as a current limiting device. Also, set a suitable value for the resistor in consideration of the LCD display grade. In addition, when connecting the logic power supply, the logic condition of the LSI inside is insecure. Therefore connect the LCD driver power supply only after resetting the logic condition of this LSI inside to the DISPOFF function. After that, the DISPOFF will cancel the function after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD driver output pins to level VSS on the DISPOFF function. After that, disconnect the logic system power after disconnecting the LCD driver power. When connecting the power supply, follow the recommended sequence shown.
VDD
VDD VSS VDD
DISPOFF
VSS V0
V0 VSS
17
NT7703
Absolute Maximum Rating*
DC Supply Voltage VDD . . . . . . . . . . . . -0.3V to +7.0V DC Supply Voltage V0 . . . . . . . . . . . . . . -0.3V to +30V Input Voltage . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Operating Ambient Temperature . . . . -30C to +85C Storage Temperature . . . . . . . . . . . . . -45C to +125C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
DC Characteristics Segment Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85C, unless otherwise noted) Parameter Operating Voltage Operating Voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current 1 Symbol VDD V0 VIH VIL VOH VOL IIH Min. 2.5 15 0.8 VDD VDD - 0.4 Typ. Max. 5.5 30 0.2 VDD +0.4 +1.0 Unit V V V V V V A A D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2 and DISPOFF pins EIO1, EIO2 pins, IOH = -0.4mA EIO1, EIO2 pins, IOL = +0.4mA D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2 and DISPOFF pins, VI = VDD D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2 and DISPOFF pins, VI = VSS V0 = +30.0V k A mA mA mA V0 = +20.0V VSS pin, Note 1 VDD pin, Note 2 VDD pin, Note 3 V0 pin, Note 4 Y1 - Y160 pins, V O N = 0.5V Condition
Input leakage current 2
IIL
-
1.0 1.5 -
-1.0 1.5 2.0 5.0 2.0 8.0 1.0
Output resistance Stand-by current Consumed current (1) (Deselection) Consumed current (2) (Selection) Consumed current Note:
RON ISB IDD1 IDD2 I0 -
1. VDD = +5.0V, V0 = +30V, VI = VSS 2. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, No-load, EI = VDD The input data is turned over by the data taking clock (4-bit parallel input mode) 3. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, No-load. EI = VSS The input data is turned over by the data taking clock (4-bit parallel input mode) 4. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, fLP = 41.6kHz. fFR = 80 Hz, No-load The input data is turned over by the data taking clock (4-bit parallel-input mode)
18
NT7703
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V, and TA = -30 to +85C, unless otherwise noted) Parameter Operating Voltage Operating Voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current 1 Symbol VDD V0 VIH VIL VOH VOL IIH Min. 2.5 15 0.8 VDD VDD - 0.4 Typ. Max. 5.5 30 0.2 VDD +0.4 +1.0 Unit V V V V V V A A D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2 and DISPOFF pins EIO1, EIO2 pins, IOH = -0.4mA EIO1, EIO2 pins, IOL = +0.4mA D0 - 6, LP, L/R, FR, MD, S/C and DISPOFF pins, VI = VDD D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2 and DISPOFF pins, VI = VSS V0 = +30.0V k A A A V0 = +20.0V VSS pin, Note 1 VDD pin, Note 2 V0 pin, Note 2 Y1 - Y160 pins, V O N = 0.5V Condition
Input leakage current 2
IIL
-
1.0 1.5 -
-1.0 1.5 2.0 5 80 160
Output resistance Stand-by current Consumed current (1) Consumed current (2) Note:
RON ISB IDD I0 -
1. VDD = +5.0V, V0 = +30V, VI = VSS 2. VDD = +5.0V, V0 = +30V, fLP = 41.6KHz, fFR = 80Hz, case of 1/480 duty operation, No-load
19
NT7703
AC Characteristics Segment Mode 1 (VSS = V5 = 0V, VDD = 4.5 - 5.5V, V0 = 15 to 30, and TA = -30 to +85C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock rise time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Note: 1. Take the cascade connection into consideration. 2. (Tck - tWCKII - twckl)/2 is the maximum in the case of high speed operation. Symbol tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3 21 100 1.2 Min. 71 23 23 10 20 23 0 25 25 25 Typ. 40 1.2 1.2 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s CL = 15pF CL = 15pF CL = 15pF Note 2 Note 2 Condition tr, tf 10ns, Note 1
20
NT7703
Segment Mode 2 (VSS = V5 = 0V, VDD = 2.5 - 4.5V, V0 = 15 to 30, and TA = -30 to +85C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock fall time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Note: 1. Take the cascade connection into consideration. 2. (tCK - tWCKII - tWCKL)/2 is the maximum in the case of high speed operation. Symbol tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3 36 100 1.2 Min. 125 51 51 30 40 51 0 51 51 51 Typ. 78 1.2 1.2 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s CL = 15pF CL = 15pF CL = 15pF Note 2 Note 2 Condition tr, tf 11ns, Note 1
21
NT7703
Timing waveform of the Segment Mode
tWLPH
LP
tLD tLS
tSL
tLH tWCKH
tWCKL
XCK
tr
tr tWCK
tDS
tDH
D0 - D7
LAST DATA
TOP DATA
tWDL
tSD
DISPOFF
LP
1 2 n
XCK
tS
EI
tD
EO
n: 4-bit parallel mode 40 8-bit parallel mode 20
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y160
22
NT7703
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V and TA = -30 to +85C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Data setup time Data hole time Input signal rise time Input signal fall time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Symbol tWLP tWLPH 30 tSU tH tr tf tSD tWDL tDL tpd1, tpd2 tpd3 100 1.2 30 50 50 50 200 1.2 1.2 ns ns ns ns ns ns s ns s s CL = 15pF CL = 15pF CL = 15pF Min. 250 15 Typ. Max. Unit ns ns Condition tr, tf 20ns VDD = +5.0V 10% VDD = +2.5 - +4.5V
23
NT7703
Timing Characteristics of Common Mode
tWLP
LP
tr
tWLPH tSU
tf tH
EIO2 (D7)
tDL
EIO1
tWDL tSD
DISPOFF
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y160
L/R = "L"
24
NT7703
Application Circuit (for reference only)
SEG640 SEG639
EIO1
Y1 - Y160
FR LP DISPOFF XCK
MD S/C L/R D0 - D7 EIO2
EIO1
Y1 - Y160
FR LP DISPOFF
MD S/C L/R D0 - D7 EIO2
640*480 DOT MATRIX LCD PANEL
XCK
EIO1
Y1 - Y160
FR LP DISPOFF XCK
MD S/C L/R D0 - D7 EIO2
EIO1
Y1 - Y160
SEG3 SEG2 SEG1 C O M 4 7 9 C O M 4 8 0
MD FR LP DISPOFF XCK S/C L/R D0 - D7 EIO2
C O M 1
C O M 2
C O M 3
Y1 - Y160
Y1 - Y160
XCK
XCK
Y1 - Y160
DISPOFF
NT7703*3
D0 - D7
D0 - D7
DISPOFF
D0 - D7
EIO1
EIO2
EIO1
EIO2
EIO1
DISPOFF
EIO2
S/C
S/C
S/C
L/R
L/R
L/R
MD
MD
MD
XCK
LP
LP
FR
FR
FR
LP
(case of 1/n bias)
YD
FR
XCK
V1 V0
V2
V3
V4
VSS V0 R R (n-4)R R R
DISPOFF
LCD controller
Note: V0-V1>1.5V
V5
VDD
VSS
25
XD0 - XD7
LP
NT7703*4
/8
/5 /5
/8
NT7703
Bonding Diagram
8168um
272 x
Y
145 x x
273
x
144
Dummy Pad
NT7703
288 x 1
ALK_L
(0,0)
X
1168um
129 x 128
x
ALK_R
Pad Location
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Designation V0L V0L V0L V0L V0L V0L V0L V12L V12L V12L V12L V12L V43L V43L V43L V43L V43L V5L V5L V5L V5L V5L VSS VSS VSS VSS VSS VSS VSS VSS X -3820 -3750 -3690 -3630 -3570 -3510 -3450 -3390 -3330 -3270 -3210 -3150 -3090 -3030 -2970 -2910 -2850 -2790 -2730 -2670 -2610 -2550 -2490 -2430 -2370 -2310 -2250 -2190 -2130 -2070 Y -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 Pad No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Designation VSS VSS VSS VSS VSS VSS VSS VSS VSS L/R L/R VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD S/C S/C EIO2 X -2010 -1950 -1890 -1830 -1770 -1710 -1650 -1590 -1530 -1470 -1410 -1350 -1290 -1230 -1170 -1110 -1050 -990 -930 -870 -810 -750 -690 -630 -570 -510 -450 -390 -330 -270 Y -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521
26
NT7703
Pad Location (continued)
Pad No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Designation EIO2 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 XCK XCK DISPOFF DISPOFF LP LP EIO1 EIO1 FR FR MD MD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS X -210 -150 -90 -30 30 90 150 210 270 330 390 450 510 570 630 690 750 810 870 930 990 1050 1110 1170 1230 1290 1350 1410 1470 1530 1590 1650 1710 1770 1830 1890 1950 2010 2070 2130 Y -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 139 139 140 Designation VSS VSS VSS VSS VSS VSS V5R V5R V5R V5R V5R V43R V43R V43R V43R V43R V12R V12R V12R V12R V12R V0R V0R V0R V0R V0R V0R V0R Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 X 2190 2250 2310 2370 2430 2490 2550 2610 2670 2730 2790 2850 2910 2970 3030 3090 3150 3210 3270 3330 3390 3450 3510 3570 3630 3690 3750 3820 4030 4030 4030 4030 4030 4030 4030 4030 4030 4030 4030 4030 Y -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -450 -390 -330 -270 -210 -150 -90 -30 30 90 150 210
27
NT7703
Pad Location (continued)
Pad No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Designation Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 X 4030 4030 4030 4030 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 Y 270 330 390 450 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 Pad No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 Designation Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 Y91 Y92 X 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 Y 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529
28
NT7703
Pad Location (continued)
Pad No. 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 Designation Y93 Y94 Y95 Y96 Y97 Y98 Y99 Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 X -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 Y 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 Pad No. 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 Designation Y128 Y129 Y130 Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 ALK_L ALK_R X -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -4030 -4030 -4030 -4030 -4030 -4030 -4030 -4030 -4030 -4030 -4030 -4030 -4030 -4030 -4030 -4030 -3921 3921 Y 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -534 -534
29
NT7703
Dummy Pad Location (Total: 6 pin)
NO. 1 2 3 X 4030 4030 3880 Y -520 520 529 NO. 4 5 6 X -3880 -4030 -4030 Y 529 520 -520
30
NT7703
Package Information
A1 A2 D1 128m1n1 D2 D1 A1 A2
C1 n1 D1 D2 m1 n1 m2 n1 4n1m2 m3 m1 m2 D1 C1 H J B D1 C3 38m1n2 (L) D2 50m3n2 n2 m1 2m2n1
C2
C1 D1 D2
16n1m1 n1
r
NT7703
m2
r m3 m1 m1 n2 C3 D2 38m1n2 (R) D1 B H J m2
16n1m1 n1
D1 C1
Chip Outline Dimensions
Symbol A1 A2 B C1 C2 C3 D1 D2 Dimensions in um 204 54 264 64 55 63 70 60 Symbol H J m1 m2 m3 n1 n2 r Dimensions in um 50 163 39 55 38 72 90 35
unit: um
31
NT7703
TCP Pin Layout
DUMMY DUMMY DUMMY DUMMY Y1 Y2 Y3 Y5 Y4 Y6 27 28 29 30 31 32
26 25 24 23 22 21 20 19 18
V0R V12R V43R VSS(V5R) MD FR EIO1 LP DISPOFF XCK D7 D6 D5 D4 D3 D2 D1 D0 EIO2 S/C VDD L/R VSS(V5L) V43L V12L V0L
NT7703
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Y78 Y79 Y80 Y81 Y82 Y83
104 105 106 107 108 109
Y155 Y156 Y157 Y158 Y159 Y160 DUMMY DUMMY DUMMY DUMMY
181 182 183 184 185 186
(COPPER SIDE VIEW)
32
NT7703
External View of TCP Pins
N T7703H - B 18 TA
H 03 77 NT
B T -A
18
33
NT7703
Cautions concerning storage: 1. When storing the product, it is recommended that it be left in its shipping package. After the seal of the packing bag has been broke, store the products in a nitrogen atmosphere. 2. Storage conditions : Storage state unopened (less than 90 days) After seal of broken (less than 30 days) Storage conditions Temperature: 5 to 30; humidity: 80%RH or less Room temperature, dry nitrogen atmosphere
3. Don't store in a location exposed to corrosive gas or excessive dust. 4. Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature. 5. Don't store the product such that it is subjected to an excessive load weight, such as by stacking. 6. Deterioration of the plating may occur after long-term storage, so special care is required. It is recommended that the products be inspected before use.
34
NT7703
Tray Information
f e
c
W1
W2
T2
T1
X
X
d
g h
W1 W2 g h T2 T1 a b e f
SECTION X-X
Tray Outline Dimensions
Symbol a b c d e f Dimensions in mm 1.50 2.67 8.50 10.90 1.60 1.40 Symbol g h W1 W2 T1 T2 Dimensions in mm 0.64 4.20 76.0 68.0 71.0 68.3
SECTION Y-Y
H30-33459-25
625=150
unit: mm
35
NT7703
Ordering Information
Part No. NT7703H-BDT NT7703H-TAB18 Package Au bump on chip tray TCP Form
36
NT7703
Product Spec. Change Notice
NT7703 Specification Revision History Version 1.0 0.2 0.1 0.0 Content TCP and tray information addition (Page 33 - 36) Gold Bump Size revision (Page 31) m1: 45 39, m2: 58 55 Pad Location Addition Original Date Dec. 2001 Sep. 2001 Nov. 2000 Nov. 2000
37

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